RF:RF-LLRFUConvFE

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Introduction

LLRFUpConv is responsible to up-convert the Intermediate Frequency (IF) signal from the LLRF system control output to RF signal, generate the Local Oscillator (LO) signal for both up and down-converters from Master Oscillator (MO) signal, and the clock signal for the main processor.

General description

LLRFUpConv is a four-channel up-converter that converts the IF input signal (20MHz) to the RF output signal (500MHz) by mixing with the LO signal (480 MHz). A frequency divider is used to obtain 10 MHz, 20 MHz, and 80 MHz (Clock) LVTTL signals for external devices from MO signal, as well as to obtain IF signal to generate LO by mixing with MO signal. Additional LO signals are provided as a reference for the down-converter. The LO and RF Drive signals are filtered by narrowband filters. Monitoring ports are provided in the Front Panel through SMA connectors. It requires a +3.3V, +5V, +12V, and -5V DC power supply. In addition, there are pin switches that interlock the RF Outputs for the equipment protection system (EPS) from FIM (Fast Interlock Module) of the LLRF. The simplified diagram with the main components and ports is shown in Fig. 1.

Figure 1: Up Conversion block diagram.

Versions Control

Table 1: RF-LLRFUConvFE version control.
Version Date Description
V1I1 First assembly
V1I2 Changed Valon 3010 to Valon 3010a, changed Valon and Split Board connections

The schematic, bill of materials, and all other files related to this crate can be found at:
\\centaurus\LNLS\Grupos\RF\Sirius DOC_TEC_RF\Sirius_DOC_TEC_RF\LLRF_Rack\Crates\LLRF_UpConversion

Devices in use

Table 2: RF-LLRFUConvFE devices.
Device # Version Device Name Location
001 V1I2 RA-RaBO01:RF-LLRFUConvFE Booster LLRF Rack
002 V1I1 RA-RaSIA01:RF-LLRFUConvFE Storage Ring A LLRF Rack

Crate Panels

Figure 2: Up Convertion Front End front panel art.
Figure 3: Up Convertion Front End rear panel art.

Device PVs

There are no PVs associated with this device.

Issue

The frequency divider was changed for a newer version that is more robust in Version V1I2 and it avoided some clock “loss” problem during system operation.